Digital adjustable chip oscillator

ABSTRACT

A digital adjustable chip oscillator comprising: a voltage control oscillator generating an oscillation signal, receiving a control voltage to adjust the frequency of the oscillation signal, and receiving an operating voltage to stabilize the frequency of the oscillation signal; a reference voltage circuit generating a reference voltage; a voltage regulation circuit receiving the reference voltage and generating the operating voltage; a digital tuning circuit receiving a digital code to adjust the control voltage and receiving the operating voltage to stabilize the control voltage; a frequency detector receiving the oscillation signal, a first reference signal with a first frequency, and a second reference signal with a second frequency, wherein when the frequency of the oscillation signal lies between the first frequency and the second frequency, the frequency detector will output a high voltage comparison signal, otherwise the frequency detector will output a low voltage comparison signal; a programmable counter receiving a clock signal to trigger the counting and generating the digital code; a programmable controller receiving the high voltage comparison signal to generate an enable signal directing the frequency detector to hold the high voltage comparison signal and directing the programmable counter to stop counting and hold the digital code; and a programmable memory receiving the enable signal to record the digital code.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates in general to an oscillator, andmore specifically to a digital adjustable chip oscillator.

[0003] 2. Description of the Related Art

[0004] In wireless communication systems, there is a necessity for thephase-lock loop circuit to synchronize with signals from other circuits.In general, the phase-lock loop circuit needs a quartz oscillatorserving as an oscillation source. Under development of the integratedcircuits technology, it is feasible to lower the cost by integratingexternal components into a chip and decrease the number of external pinsneeded. Therefore, there is a necessity to provide a digital adjustablechip oscillator having digital tuning function, self-test systems, andpower save modes.

SUMMARY OF THE INVENTION

[0005] The present invention provides a digital adjustable chiposcillator comprising a voltage control oscillator generating anoscillation signal, receiving a control voltage to adjust the frequencyof the oscillation signal, and receiving an operating voltage tostabilize the frequency of the oscillation signal, a reference voltagecircuit generating a reference voltage, a voltage regulation circuitreceiving the reference voltage and generating the operating voltage, adigital tuning circuit receiving a digital code to adjust the controlvoltage and receiving the operating voltage to stabilize the controlvoltage, a frequency detector receiving the oscillation signal, a firstreference signal with a first frequency, and a second reference signalwith a second frequency, wherein when the frequency of the oscillationsignal lies between the first frequency and the second frequency, thefrequency detector outputs a high voltage comparison signal, otherwisethe frequency detector outputs a low voltage comparison signal, aprogrammable counter receiving a clock signal to trigger the countingand generating the digital code, a programmable controller receiving thehigh voltage comparison signal to generate an enable signal directingthe frequency detector to hold the high voltage comparison signal anddirecting the programmable counter to stop counting and hold the digitalcode, and a programmable memory receiving the enable signal to recordthe digital code.

[0006] The present invention provides another digital adjustable chiposcillator comprising: a voltage control oscillator generating anoscillation signal and receiving a control voltage to control thefrequency of the oscillation signal, a frequency-to-voltage converterreceiving the oscillation signal and generating a loop voltage accordingto an operating voltage and a first voltage, an active comparison filterreceiving the loop voltage, receiving a second voltage, and generatingthe control voltage, and a first programmable controller receiving afirst digital code, receiving the operating voltage, and generating thesecond voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description, given by way of example andnot intended to limit the invention solely to the embodiments describedherein, will best be understood in conjunction with the accompanyingdrawings, in which:

[0008]FIG. 1 is a block diagram illustrating the digital adjustable chiposcillator in the first embodiment;

[0009]FIG. 2 is a schematic diagram illustrating the circuit of thevoltage control oscillator 10;

[0010]FIG. 3 is a graph illustrating the voltage-to-time wave of thevoltage control oscillator 10;

[0011]FIG. 4 is a schematic diagram illustrating the circuit of thedigital adjustable chip oscillator;

[0012]FIG. 5A is a schematic diagram illustrating the switch capacitancevoltage control oscillator 10;

[0013]FIG. 5B is a schematic diagram illustrating the switch resistancevoltage control oscillator 10;

[0014]FIG. 6 is a schematic diagram illustrating the digital tuningcircuit 80 a;

[0015]FIG. 7 is a schematic diagram illustrating the circuit of thedigital-code-to-sign-code decoder 126;

[0016]FIG. 8 is a graph illustrating the test results of the voltagecontrol oscillator 10 when the voltage source varies;

[0017]FIG. 9 is a graph illustrating the test results of the voltagecontrol oscillator 10 when the digital code varies;

[0018]FIG. 10 is a schematic diagram illustrating the digital tuningcircuit 80 b;

[0019]FIG. 11 is a schematic diagram illustrating the voltage regulationcircuit 70;

[0020]FIG. 12 is a schematic diagram illustrating the reference voltagecircuit 75;

[0021]FIG. 13 is a schematic diagram illustrating the circuit of theprescaler 85;

[0022]FIG. 14 is a block diagram illustrating the digital adjustablechip oscillator and the built-in self-test system;

[0023]FIG. 15 is a flowchart illustrating the self-test system;

[0024]FIG. 16 is a schematic diagram illustrating the circuit of thefrequency detector 20;

[0025]FIG. 17 is a schematic diagram illustrating the circuit of theD-type flip-flop (DFF);

[0026]FIG. 18A is a schematic diagram illustrating the switchcapacitance circuit of resistors;

[0027]FIG. 18B is a schematic diagram illustrating the switchcapacitance circuit of low-pass filters;

[0028]FIG. 19 is a schematic diagram illustrating the circuit of thecomparator;

[0029] FIGS. 20A-20C are graphs illustrating the voltage-to-time wave ofthe frequency detector 20;

[0030]FIG. 21 is a schematic diagram illustrating the circuit of theprogrammable counter 60;

[0031]FIG. 22 is a graph illustrating the wave of the programmablecounter 60;

[0032]FIG. 23 is a schematic diagram illustrating the programmable fuse55;

[0033]FIG. 24 is a structural diagram illustrating the poly-silicon fuse(PO2);

[0034] FIGS. 25-29 are structural diagrams illustrating the programmablegate writer 50;

[0035]FIG. 30 is a block diagram illustrating the chip oscillator withloop circuits 200 in the second embodiment;

[0036]FIG. 31A is a schematic block diagram illustrating thefrequency-to-voltage converter 110;

[0037]FIG. 31B is a schematic diagram illustrating the circuit of thefrequency-to-voltage converter 110;

[0038]FIG. 32 is a graph illustrating the frequency-to-voltage wave ofthe frequency-to-voltage converter 110;

[0039]FIG. 33 is a graph illustrating the wave of the delay circuit 160;

[0040]FIG. 34 is a schematic diagram illustrating the delay circuit 160;

[0041]FIG. 35 is a schematic diagram illustrating the circuit of thesecond programmable controller 172;

[0042]FIG. 36 is a schematic diagram illustrating the circuit of theactive comparison filter 120;

[0043]FIG. 37 is a schematic diagram illustrating the circuit of thevoltage limiter 130;

[0044]FIG. 38A is a schematic diagram illustrating the voltage controloscillator 140;

[0045]FIG. 38B is a schematic diagram illustrating the circuit of thedifferential delay unit 260;

[0046]FIG. 39 is a schematic diagram illustrating the circuit of thedifferential single-end converter 142;

[0047]FIG. 40 is a schematic diagram illustrating the circuit of thefirst programmable controller 170;

[0048]FIG. 41 is a graph illustrating the test results of the voltagecontrol oscillator 140 when the digital code varies;

[0049]FIG. 42 is a graph illustrating the test results of the voltagecontrol oscillator 140 when the voltage source varies; and

[0050]FIG. 43 is a graph illustrating the frequency shift caused by thechip.

DETAILED DESCRIPTION OF THE INVENTION

[0051] The following detailed description, given by way of example andnot intended to limit the invention solely to the embodiments describedherein, will best be understood in conjunction with the accompanyingdrawings, in which:

[0052] The First Embodiment

[0053]FIG. 1 is a block diagram illustrating the digital adjustable chiposcillator in the first embodiment. As shown in FIG. 1, the digitaladjustable chip oscillator comprises a voltage control oscillator 10, avoltage regulation circuit 70, a reference voltage circuit 75, a digitaltuning circuit 80, and a prescaler 85. The voltage control oscillator isa relaxation oscillator.

[0054]FIG. 2 is a schematic diagram illustrating the circuit of thevoltage control oscillator 10. The transistors M1 and M2 form a positiveloop circuit to provide a fast switch. M1 and M2 conduct currentsmutually to cut off the positive loop circuit in half period. Thecapacitance C of the capacitor C1 is used to control the dischargingtime.

[0055] The resistances R of the resistors R1 and R2 are used to controlthe amplitudes of the oscillation signals Vout1 and Vout2. The currentsID of the transistors M3 and M4 are adjustable.

[0056]FIG. 3 is a graph illustrating the voltage-to-time wave of thevoltage control oscillator 10. In state i, the transistor M1 is turnedoff and the transistor M2 is turn on. The voltage of the oscillationsignal Vout1 is Vddx, the current of the capacitor C1 is the current IDof the transistor M3, so that the current of the transistor M2 is 21D,the sum of the current of the capacitor C1 and the current of thetransistor M4. Therefore the voltage of the oscillation signal Vout2 isVddx−2IDR. If 2IDR is smaller than the threshold voltage Vth of thetransistor M2, M2 will work in the saturation area. The voltage of nodeY is V_(y)=V_(ddx)−V_(th)−{square root}{square root over (2I_(D)/K)}wherein K is the conductance parameter of the transistor M2. Thedischarging velocity of node VX is 2ID/C. When the voltage VX lowers tothe value V_(ddx)−2I_(D)R−V_(th), in other words when the gate-to-sourcevoltage difference of the transistor M1 reaches the threshold voltage,M1 will be turned on rapidly, the oscillation signal Vout1 will belowered, the transistor M2 will be turned off, and then the voltagecontrol oscillator 10 will work in state ii. The voltage controloscillator 10 works in state ii in a similar but symmetric way comparedto state i. Derived from FIG. 3, the oscillation period T is$\begin{matrix}{{T = \frac{{- \sqrt{2{I_{D}/K}}} + {I_{D}R}}{I_{D}/C}},} & (1)\end{matrix}$

[0057] and the oscillation frequency f is $\begin{matrix}{f = {\frac{1}{T} = {\frac{1}{C( {{2R} - \sqrt{2/{KI}_{D}}} )}.}}} & (2)\end{matrix}$

[0058] Thus the oscillation frequency f can be adjusted by theresistance R1, the resistance R2, the capacitance C1, and the currentID. The voltage Vin is input into the gates of the transistors M3 and M4to control the current ID.

[0059]FIG. 4 is a schematic diagram illustrating the circuit of thedigital adjustable chip oscillator. The output buffer 12 comprising abuffer and a double-end-to-single-end converter converts the oscillationsignals Vout1 and Vout2 to a single-end voltage large enough to drivethe prescaler and other logic circuits, isolates the voltage controloscillator 10 with other circuits, provides enough power to thenext-stage circuits, and avoids affecting the normal operation of thevoltage control oscillator 10. As shown in FIG. 4, the gate of thetransistor M7 receives a power save signal PWD, turns off the transistorM6, and therefore turns off the voltage control oscillator 10. Thevoltage regulation circuit 70 provides a stable operating voltage Vddxwithout effects of temperature and voltage source. The stable operatingvoltage Vddx is used as the bias of the voltage control oscillator 10 tostabilize the oscillation frequency.

[0060]FIG. 5A is a schematic diagram illustrating the switch capacitancevoltage control oscillator 10. The switches SWC1-SWCn are used to adjustthe coupling capacitance of the capacitor C1 in FIG. 2 and control theoscillation frequency.

[0061]FIG. 5B is a schematic diagram illustrating the switch resistancevoltage control oscillator 10. The switches SWR1-SWRn are used to adjustthe resistances of the resistors R1 and R2 in FIG. 2 and control theoscillation frequency.

[0062]FIG. 6 is a schematic diagram illustrating the digital tuningcircuit 80 a. The output end VBN is coupled to the control voltages Vinof the transistors M3 and M4 of the voltage control oscillator 10. Byadjusting the input current of the transistor M10, the transistors M10,M3, and M4 work together as a current mirror to control the voltage ofthe output end VBN, control the output currents of the transistors M3and M4 of the voltage control oscillator 10, and therefore adjust theoscillation frequency of the voltage control oscillator 10. The digitaltuning circuit 80 works as a digital-to-analog converter (DAC). Byeffects of the negative loop operation of the reference voltage Vref andthe differential amplifier 101, the digital tuning circuit 80 directsthe reference current of the transistor M102 be Vref/R. In cooperationwith the current mirror comprising the transistors M102, M103, and M104,the digital tuning circuit 80 proportions the current of the output endVBN to the reference current. The transistors M110, M111, M112, and M113work together as a charge current mirror to provide charge currents 8Ip,4Ip, 2Ip, and Ip coupled to the output end VBN by connection of switchtransistors MB0, MB1, MB2, and MB3. The digital codes B0, B1, B2, and B3are used to select the corresponding bits of the charge currents. Theoperating voltages of the transistors M102, M103, M110, M111, M112,M113, and M114 are provided by the output end voltage Vddx of thevoltage regulation circuit 70. Vddx is a stable voltage source used tostabilize the current of the digital tuning circuit 80 and the outputend voltage VBN of the digital tuning circuit 80 and further stabilizethe oscillation frequency of the voltage control oscillator 10. Thetransistors M120, M121, M122, and M123 work together as a dischargecurrent mirror to provide discharge currents 8In, 4In, 2In, and Incoupled to the output end VBN by connection of switch transistors MA0,MA1, MA2, and MA3. The digital codes A0, A1, A2, and A3 are used toselect the corresponding bits of the discharge currents. The transistorM10 increases the output current by adjusting the sign codes B3, B2, B1,and B0. The transistor M10 decreases the output current by adjusting thesign codes A3, A2, A1, and A0.

[0063]FIG. 7 is a schematic diagram illustrating the circuit of thedigital-code-to-sign-code decoder 126. The decoder 126 converts thedigital codes D4, D3, D2, D1, and D0 to the sign codes B3, B2, B1, B0,A3, A2, A1, and A0. By way of DAC current mode, the digital tuningcircuit 80 adjusts the control voltage of the voltage control oscillator10. The operating voltage of the digital tuning circuit 80 is providedby the voltage regulation circuit 70, so that the control voltage of thevoltage control oscillator 10 is stable and linear. The oscillationfrequency shift caused by the manufacturing process can be compensatedto only 1 percentage of frequency error by the digital tuning circuit80.

[0064]FIG. 8 is a graph illustrating the test results of the voltagecontrol oscillator 10 when the voltage source varies. As shown in FIG.8, when the digital code is −15, 0, or 15, the oscillation frequency ofthe voltage control oscillator 10 is almost unaffected by the voltagesource Vdd.

[0065]FIG. 9 is a graph illustrating the test results of the voltagecontrol oscillator 10 when the digital code varies.

[0066]FIG. 10 is a schematic diagram illustrating the digital tuningcircuit 80 b. The function of the digital tuning circuit 80 b is similarto that of the digital tuning circuit 80 a in FIG. 6 except that thedigital codes A5, A4, A3, A2, A1, and A0 used to adjust the outputcurrents can be operated in only single direction. In other words, theoutput currents can only be increased by adjusting the digital codes A5,A4, A3, A2, A1, and A0. Both the digital tuning circuits 80 a and 80 bcan be applied to the first embodiment herein.

[0067]FIG. 11 is a schematic diagram illustrating the voltage regulationcircuit 70. The voltage regulation circuit 70 provides a stable voltagewithout effects of temperature and voltage source Vdd. The stablevoltage is provided to both the voltage control oscillator 10 and thedigital tuning circuit 80. The voltage regulation circuit 70 comprisesan operational transconductance amplifier 82, a transistor M8, and aloop circuit. The loop circuit comprises a loop resistor R3, a loopresistor R4, a compensation resistor Rz, and a compensation capacitorCc. The loop circuit detects the output current of the transistor M8 andoutputs the loop voltage to the operational transconductance amplifier82. In cooperation with the reference voltage Vref and the loop circuit,the voltage regulation circuit 70 stabilizes the output end voltagecoupled to the voltage source Vddx of the voltage control oscillator 10.The transistor M8 is a PMOS transistor, so that the highest voltagerange of the output voltage Vddx can be higher.

[0068]FIG. 12 is a schematic diagram illustrating the reference voltagecircuit 75. The reference voltage circuit 75 is a bandgap referencevoltage circuit. The reference voltage circuit 75 provides a stablereference voltage Vref without effects of temperature and voltage sourceVdd. The effects of the temperature can be lowered mainly because of thecharacteristics of the negative temperature parameter of thebase-emitter interface voltage VEB of the BJT Q1 and the characteristicsof the positive temperature parameter of ΔE_(EB). When the BJT Q1 and Q2operate in different current densities of bias, the amplifier 83 detectsthe voltage difference ΔE_(EB) and gets fixed voltage kT/q1n(R3/R1) withpositive temperature parameter. The current density of bias can bedecided by the ratio of resistances R3 to R1. By the ratio ofresistances R3 to R2, the amplifier 83 decides the fixed voltageenlargement factor of the positive temperature parameter used to balancethe negative temperature parameter of the base-emitter interface voltageof the BJT Q1, thereby obtaining a reference voltage Vref. The referencevoltage Vref=V+(R3/R2)kT/q1n(R3/R1). The currents flowing through theresistors R1 and R3 are the same, so that the base areas A1 and A2 ofthe transistors Q1 and Q2 are in an inverse proportion to the currentdensities of Q1 and Q2. The ratio of base areas A1 to A2 (A1:A2) isusually designed to be 1:3, 1:8, 1:15, 1:24, or others wherein the sumof the numerator and the denominator in each case is the square of anatural number. By this design method, the layout will be moresymmetric. The bias circuit 83A provides the bias to the amplifier 83 tocut off the source in the power save mode wherein the gates of the PMOStransistor M100 and the NMOS transistor M102 are coupled to a power savesignal PWD.

[0069]FIG. 13 is a schematic diagram illustrating the circuit of theprescaler 85. The prescaler 85 comprises a division-by-4 or-5 circuitand the prescaler circuit having three D-type flip-flops (DFF). Theprescaler controls the prescaler parameter by selecting modes.

[0070]FIG. 14 is a block diagram illustrating the digital adjustablechip oscillator and the built-in self-test system. The built-inself-test circuit is used to automatically adjust the frequency to meetthe requirement. The built-in self-test system comprises a voltagecontrol oscillator 10, a frequency detector 20, a frequency generator65, a programmable controller 40, a programmable gate writer 50, aprogrammable fuse 55, and a programmable counter 60. Both theprogrammable gate writer 50 and the programmable fuse 55 can be used asthe programmable memories herein. Both the programmable gate writer 50and the programmable fuse 55 can write, read, and load the digital codeto the frequency detector 20. The frequency detector 20 can select thedesired frequency automatically by the signals from the controller.

[0071]FIG. 15 is a flowchart illustrating the self-test system. In stepS11, the micro-controller instructs the programmable counter 60 togenerate a series of digital codes to the digital tuning circuit 80, andthe voltage control oscillator 10 generates the correspondingfrequencies. In step S12, the prescaler 85 calculates the oscillationfrequency of the voltage control oscillator 10. In step S13, thefrequency generator 65 generates two reference frequencies, respectivelyFref1 and Fref2. In step S14, the frequency detector 20 compares theoscillation frequency of the voltage control oscillator 10 with Fref1and Fref2 generated by the frequency generator. When the oscillationfrequency lies between the preset reference frequencies Fref1 and Fref2,the frequency detector 20 will output a high voltage comparison signal,otherwise the frequency detector 20 will output a low voltage comparisonsignal. In step S15, the programmable controller 40 receives the highvoltage comparison signal of the frequency detector 20 and sends a stopsignal to the frequency generator and the programmable counter 60.Therefore, the programmable counter 60 holds the digital code and sendsan enable signal to both the programmable gate writer 50 and theprogrammable fuse 55. Furthermore, the programmable gate writer 50 andthe programmable fuse 55 will execute the writing operation and load thedigital code to the digital tuning circuit 80. In step S16, theprogrammable controller 40 sends a reset signal notifying the controllerto recount. Additionally, in step S11, when the programmable controller40 receives the low voltage of the frequency detector 20, theprogrammable counter 60 will continue counting and generate the nextdigital code. Therefore, the voltage control oscillator 10 will generatethe next oscillation frequency until the oscillation frequency is in therange of the reference frequency.

[0072]FIG. 16 is a schematic diagram illustrating the circuit of thefrequency detector 20. The frequency detector 20 comprisesphase-frequency detectors 21 and 22, low-pass filters 23 and 24,comparators 25 and 26, and an exclusive gate 27. The frequency detector20 receives three input signals, a first reference signal having thefirst reference frequency Fref1, a second reference signal having thesecond reference frequency Fref2, and the test signal. The test signalis the oscillation signal of the voltage control oscillator, and it hasthe frequency Fsig. The low-pass filters 23 and 24 are used to detectthe dc components of the output signals of the phase-frequency detectors21 and 22 respectively. By this method, relationships between thefrequency of the test signal, the first reference frequency, and thesecond reference frequency can be decided. The phase-frequency detector21 comprises a D-type flip-flop DFF1, a D-type flip-flop DFF2, and anAND-gate AND1.

[0073]FIG. 17 is a schematic diagram illustrating the circuit of theD-type flip-flop (DFF). When the frequency Fref1 is higher than thefrequency Fsig, Q1 will have the main dc component; on the contrary,when the frequency Fref1 is lower than the frequency Fsig, Q2 will havethe main dc component. Similarly, when the frequency Fref2 is higherthan the frequency Fsig, Q4 will have the main dc component; on thecontrary, when the frequency Fref2 is lower than the frequency Fsig, Q3will have the main dc component.

[0074]FIG. 18A is a schematic diagram illustrating the switchcapacitance circuit of resistors. FIG. 18B is a schematic diagramillustrating the switch capacitance circuit of low-pass filters. Bycontrolling the clock signals PH1 and PH2 in FIG. 16, the capacitorsC21, C22 and the transistors M21, M22 constitute the switch capacitancelow-pass filter 21 wherein the capacitor C21, the transistor M21, andthe transistor M22 constitute an effective resistor. The effectiveresistance R=1/(C21fc). The 3 dB bandwidth of the low-pass filter w3dB=1/RC22=f(C21/C22). When operating the frequency detector 20, thefrequencies fc of the clock signals PH1 and PH2 should satisfy thefollowing condition: fc>>w3 dB. The low-pass filter 23 integrates thedetection signals Q1 and Q2 and outputs a dc voltage level. Thecomparator 25 receives the dc voltage level and outputs a comparisonsignal having a logic level. The logic level represents the magnituderelationship of the oscillation frequency Fsig and the referencefrequency Fref1.

[0075]FIG. 19 is a schematic diagram illustrating the circuit of thecomparator. The phase-frequency detector 22, the low-pass filter 24, andthe comparator 26 generate the comparison signal of the referencefrequency Fref2 and the oscillation frequency Fsig. The comparisonsignals of the comparators 25 and 26 are input into the exclusive gate27. When the oscillation frequency Fsig lies between the referencefrequency Fref1 and the reference frequency Fref2, the exclusive gate 27will output 1, such that the oscillation frequency Fsig meets therequirement. Otherwise, the exclusive gate 27 will output 0, wherein theoscillation frequency Fsig does not meet the requirement.

[0076] FIGS. 20A-20C are graphs illustrating the voltage-to-time wave ofthe frequency detector 20. As shown in FIG. 20A, when the oscillationfrequency Fsig is lower than both the reference frequencies Fref1 andFref2, the output end OUT1 of the comparator 25 is low-level, the outputend OUT2 of the comparator 26 is low-level, and the output end OUT ofthe exclusive gate 27 is low-level. As shown in FIG. 20B, when theoscillation frequency Fsig is higher than both the reference frequenciesFref1 and Fref2, the output end OUT1 of the comparator 25 is high-level,the output end OUT2 of the comparator 26 is high-level, and the outputend OUT of the exclusive gate 27 is low-level. As shown in FIG. 20C,when the oscillation frequency Fsig lies between the referencefrequencies Fref1 and Fref2, the output end OUT1 of the comparator 25 ishigh-level, the output end OUT2 of the comparator 26 is low-level, andthe output end OUT of the exclusive gate 27 is high-level.

[0077]FIG. 21 is a schematic diagram illustrating the circuit of theprogrammable counter 60. The programmable counter comprises anasynchronous counter having positive edge trigger D-type flip-flops(DFF). The QB of each flip-flop is looped to D of each flip-flop. The Qof each flip-flop is input into CK of the flip-flop at the next stage.The reference operating frequency REFCLK should be lower than the outputfrequency of the voltage control oscillator 10, so that the self-testsystem will have enough time to finish the whole operation before thenext digital code is generated.

[0078]FIG. 22 is a graph illustrating the wave of the programmablecounter 60. The outputs C0-C6 of the programmable counter 60 are used tochange the digital codes of the digital tuning circuit 80 and sweep thefrequency of the digital adjustable chip oscillator 12. The main objectof the programmable controller 40 is to control the writing operation.The frequency detector 20 detects the frequency of the digitaladjustable chip oscillator 12. When the frequency of the digitaladjustable chip oscillator 12 lies between the two referencefrequencies, the programmable controller 40 will send a stop signal tothe programmable counter 60. Therefore, the programmable counter 60 willstop the operation, the output of the programmable counter 60 will befixed at a digital code, and the programmable gate writer 50 and theprogrammable fuse 55 will be allowed to perform the writing operation.At the same time, the programmable controller 40 will send a resetsignal notifying the controller to recount.

[0079]FIG. 23 is a schematic diagram illustrating the programmable fuse55. As shown in FIG. 23, the programmable fuse 55 comprises a pluralityof decoders (DR) and a plurality of poly-silicon fuses (PO2).

[0080]FIG. 24 is a structural diagram illustrating the poly-silicon fuse(PO2). The fuse PO2 uses a layer of poly-silicon or a layer of metal.The layers are 1 to 5 times the size of the unit square of materialused. If 5 to 15 volts of the conductance dc voltage are input into thepoly-silicon fuse, the poly-silicon fuse will burn out. By thischaracteristic, the poly-silicon fuse achieves the writing operation. Aswell as the poly-silicon fuse, the programmable gate writer 50 can alsoperform the writing operation. Compared with the poly-silicon fuse, theprogrammable gate writer 50 works like an electrical erasableprogrammable read-only memory (EEPROM).

[0081] FIGS. 25-29 are structural diagrams illustrating the circuit ofthe programmable gate writer 50. The programmable gate writer 50 can bemanufactured using the standard CMOS manufacturing process. FIG. 25shows the F/N tunneling floating gate transistor. The gate of the PMOStransistor M1 and the gate of the NMOS transistor M2 are coupledtogether to form a floating gate. The drain and the source of the PMOStransistor M1 are coupled together to form a capacitor. The drain andthe source of the NMOS transistor M2 are coupled together to form acapacitor. To satisfy the conditions of Fowler-Nordheim tunneling, theratio of the gate capacitance CGP of the PMOS transistor M1 to the gatecapacitance CGN of the NMOS transistor M2 should be larger than 3. FIG.26 shows the hot electron floating gate transistor. To satisfy theconditions of hot electrons in the NMOS tunnel, the ratio of the gatecapacitance CGP of the PMOS transistor M1 to the gate capacitance CGN ofthe NMOS transistor M2 should be smaller than 3. FIG. 27 shows thefloating gate transistor performing access. FIG. 28 shows the F/Ntunneling floating gate transistor performing deletion. FIG. 29 showsthe hot electron floating gate transistor performing deletion.Additionally, the advantages of the standard CMOS manufacturing processare as follows: (1) the circuit area can be decreased; (2) the powerconsumption of the circuit can be decreased; (3) the record of thewriting operation can be read; (4) the record of the writing operationcan be written; (5) the record of the writing operation can be deleted;and (6) the circuit can be integrated into other commonly used digitalCMOS circuits.

[0082] The Second Embodiment

[0083]FIG. 30 is a block diagram illustrating the chip oscillator withloop circuits 200 in the second embodiment. The chip oscillator withloop circuits 200 has a loop control circuit comprising afrequency-to-voltage converter 110, an active comparison filter 120, avoltage limiter 130, a voltage control oscillator 140, a buffer 142, aprescaler 150, a delay circuit 160, a first programmable controller 170,a second programmable controller 170, a voltage regulation circuit 180,and a reference voltage circuit 182. The frequency-to-voltage converter110 converts the frequency of the oscillation signal of the voltagecontrol oscillator 140 to a loop voltage Vfed. Using the negative loopcircuit, the loop voltage Vfed follows the reference voltage Vreg.Therefore the output frequency fout is controlled by the referencevoltage. When the loop circuit is stable, the output frequency

fout=N*Vreg/Kfvc  (1).

[0084] And the reference voltage Vref can be changed by the programmabletuning circuit 170. N is the prescaler parameter of the prescaler 150.Kfvc is the conversion gain of the frequency-to-voltage converter 110.The lock time of the chip oscillator with loop circuits herein is veryshort compared to the frequency synthesizer of the phase-lock loopcircuit. The frequency synthesizer of the phase-lock loop circuitcompares the output frequency of the loop circuit with the referencefrequency and compares the output phase of the loop circuit with thereference phase.

[0085]FIG. 31A is a schematic block diagram illustrating thefrequency-to-voltage converter 110. FIG. 31B is a schematic diagramillustrating the circuit of the frequency-to-voltage converter 110. Thefrequency-to-voltage converter 110 comprises: capacitors C1, C2, and C3;a reversed-phase amplifier 210; switches S1, S2, and S3; a voltagesource Vddx; and a voltage control current source 212. Thefrequency-to-voltage converter 110 is mainly adjusted by controlling theelectric charge distribution of the switch capacitance and the frequencyof the input signal of the switch.

[0086]FIG. 32 is a graph illustrating the frequency-to-voltage wave ofthe frequency-to-voltage converter 110. The output voltage Vg5 of theintegrator controls the discharge balance current gmvg. Thetransconductance gm is decided by the ratio of the transistor M5 to thecurrent mirrors M7 and M8, which is K=(W/L)7/(W/L)8. In the temporalphase T1, the switch S1 turns on and the capacitor C1 charges to Vddx.In the temporal phase T2, the switches S2 and S3 turn on, the capacitorsC1 and C2 couple with the virtual shortcut voltage Vref, and the losselectric charges of the capacitor C1 flow into the capacitors C2 and C3wherein the loss electric charges Q=C1(Vddx−Vref). In stable state, theelectric charges flowing into the capacitor C3 are 0, so the wholeelectric charges flow into the capacitor C2. Also, in stable state, theelectric charges in the capacitor C2 are electrically balanced. FromQ=I7*T1,

I 7=C 1*(Vddx−Vref)/T 1  (2).

[0087] The output voltage Vout is directly proportional to the outputcurrent Iout, and the output current Iout is directly proportional tothe currents of the transistors M5 and M7.

[0088] Therefore,

Vout=K*R*C 1(Vref−Vg)f1  (3).

F1=1/T 1

[0089] To be operated under a low voltage, the transmission gates of thetransistors M9 to M10, M11 to M12, and M13 to 14 are used as switches tolower the impedance and increase the conductance voltage range. To befully charged and discharged, the input signals of thefrequency-to-voltage converter 110 should satisfy the condition that theperiod of the temporal phase T1 is much larger than the period of thetemporal phase T2.

[0090]FIG. 33 is a graph illustrating the wave of the delay circuit 160.The delay circuit 160 performs the conversion of the operating period ofthe oscillation signal.

[0091]FIG. 34 is a schematic diagram illustrating the delay circuit 160.From the above equation (3), the output voltage is directly proportionalto the operating frequency. The operating voltage Vddx and the virtualshortcut voltage Vref are both fixed voltage without effects of theoperating voltage and the manufacturing process. Therefore, theconversion characteristic of the frequency-to-voltage converter 110 isnearly linear.

[0092]FIG. 35 is a schematic diagram illustrating the circuit of thesecond programmable controller 172. The second programmable controller172 comprises a plurality of current mirrors and a plurality of switcheswherein the gates of the plurality of current mirrors are coupled to thegate of the transistor M5 or M8 of the frequency-to-voltage converter110. Therefore, the current generated by each current mirror is amultiple of the balance current of the transistor M7 wherein themultiplication factor corresponds to the bit of the digital code. Theplurality of switches coupled to the output ends of the correspondentplurality of current mirrors and the output ends of thefrequency-to-voltage converter 110 receive the digital code to selectthe plurality of current mirrors, adjust K in the equation (3), andadjust Kfvc in the equation (1). The second programmable tuner 172 canbe used as a fine-tuner in the digital adjustable chip oscillator.

[0093]FIG. 36 is a schematic diagram illustrating the circuit of theactive comparison filter 120. The active comparison filter 120 comprisesan operational amplifier 240, resistors R1 and R2, and capacitors C1 andC2. The active comparison filter 120 is a proportional integral filterused to compare the loop voltage Vfed of the frequency-to-voltageconverter 110 with the reference voltage Vref and stabilize the loopcircuit. The shift of the operational amplifier 240 can be compensatedby the reference voltage adjusted by the programmable tuning circuit170. The resistor R2, the capacitor C1, and the capacitor C2 constitutea filter used to filter the switch noise of the frequency-to-voltageconverter 110, provide the voltage control oscillator 140 with a pure dccontrol voltage, and maintain the stability of the loop circuit. Usingthe active comparison filter 120, the tuning range of the input voltageof the voltage control oscillator 140 can be increased. The output ofthe active comparison filter 120 is an analog voltage signal, so thereis a possibility that the output voltage is lower than the lowestcontrol voltage of the voltage control oscillator 140. In suchsituation, the voltage control oscillator 140 will stop oscillating.

[0094]FIG. 37 is a schematic diagram illustrating the circuit of thevoltage limiter 130. The voltage limiter 130 converts the output lowvoltage or the output high voltage of the active comparison filter 120to a voltage in the tuning range of the voltage control oscillator 140.For example, when the reference voltage Vref is higher than the loopvoltage Vfed and the active comparison filter 120 outputs a low voltage,the voltage limiter 130 will convert the low voltage to the desiredinput voltage of the voltage control oscillator 140. Therefore, thevoltage control oscillator 140 can adjust the input voltage andoscillate according to it. In this way, it is easier to have the desiredhigh-precision output frequency.

[0095]FIG. 38A is a schematic diagram illustrating the voltage controloscillator 140. The voltage control oscillator 140 comprises a ringoscillator having 4-stage differential delay units.

[0096]FIG. 38B is a schematic diagram illustrating the circuit of thedifferential delay unit 260. The delay time of the differential delayunit 260 is controlled by the bias current of the transistor M1, inother words, the oscillation frequency of the voltage control oscillator140 is controlled by the bias current of the transistor M1. Theoscillation frequency f_(OSC)=1/(2Nt_(d))≅I_(ss)/2NC_(L)V_(SW) whereinCL is the load capacitance (parasitical capacitance) of eachdifferential delay unit 260. The control voltage Vcnt decides thecurrent ISS of the transistor M1 and also controls the oscillationfrequency. The oscillation amplitude VSW of the differential delay unit260 is decided and limited by the bias Vb generated by the replicacircuit (not shown in the drawings) of the differential delay unit and anegative loop circuit (not shown in drawings). The differential delayunit transistors M6, M7, M8, and M9 constitute the symmetric load havingthe symmetric current-to-voltage conversion characteristics and avoidingthe common mode noise well. The cross coupling transistors M4 and M5 canincrease the symmetry of load and decrease the noise of phase. Thesources of the load transistors M4, M5, M6, M7, and M8 are coupled tothe stable operating voltage Vddx. Therefore, the oscillation frequencyof the voltage control oscillator 140 is more stable and will notaffected by the voltage source

[0097]FIG. 39 is a schematic diagram illustrating the circuit of thedifferential single-end converter 142. The differential single-endconverter 142 converts the differential signal of the voltage controloscillator 140 to a single-end signal. The differential single-endconverter 142 adds a buffer at the output stage to provide the prescaler150 and the delay circuit 160 with a full amplitude oscillation signal.Another object of the differential single-end converter 142 is toisolate the output end of the voltage control oscillator 140 and avoidaffecting the normal operation of the voltage control oscillator 140.

[0098]FIG. 40 is a schematic diagram illustrating the circuit of thefirst programmable controller 170. The first programmable controller 170comprises: a resistor serial having a plurality of resistors R1 to R17,coupled to the operating voltage Vddx, and generating the second voltageVreg from the output end; a plurality of switches S1 to S16 coupled tothe corresponding connection points of the plurality of resistors andthe output end of the first programmable controller; and a decoder 280receiving the first digital code to select the corresponding switch andadjust the second voltage Vreg to meet the requirement of theoscillation frequency. The voltage regulation circuit 180 receives thereference voltage Vref and generates the operating voltage Vddx, so thatboth the operating voltage Vddx and the second reference voltage Vregare stable voltages without effects of the voltage source. The firstprogrammable controller 170 can be used as a coarse-tuner in the digitaladjustable chip oscillator.

[0099]FIG. 41 is a graph illustrating the test results of the voltagecontrol oscillator 140 when the digital code varies. As shown in FIG.41, the conversion relationship of the oscillation frequency and thedigital code is linear. The frequency shifts slightly among the voltagecontrol oscillators 140 of different chips. The frequency shifts can beadjusted by the second programmable controller 172.

[0100]FIG. 42 is a graph illustrating the test results of the voltagecontrol oscillator 140 when the voltage source varies. As shown in FIG.42, the voltage source affects the oscillation frequency to a verylimited extent.

[0101]FIG. 43 is a graph illustrating the frequency shift caused by thechip. As shown in FIG. 43, for different chips, the frequency shifts areno more than 10 percentages when the voltage source Vdd is 3 volts and3.6 volts respectively.

[0102] The test structures of the first and second embodiments are thesame. In the test structure of the second embodiment, the chiposcillator with loop circuits 200 is integrated into the test structurein FIG. 9. The steps of testing and writing in the second embodiment arethe same as those in the first embodiment. The programmable counter 60in FIG. 9 outputs the digital code to the first programmable controllerand the second programmable controller and thus adjusts the oscillationfrequency to be the desired frequency.

[0103] While the invention has been described by way of example and interms of the preferred embodiments, it is to be understood that theinvention is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangementsas would be apparent to those skilled in the art. Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

What is claimed is:
 1. A digital adjustable chip oscillator, comprising:a voltage control oscillator generating an oscillation signal, receivinga control voltage to adjust the frequency of the oscillation signal, andreceiving an operating voltage to stabilize the frequency of theoscillation signal; a reference voltage circuit generating a referencevoltage; a voltage regulation circuit receiving the reference voltageand generating the operating voltage; a digital tuning circuit receivinga digital code to adjust the control voltage and receiving the operatingvoltage to stabilize the control voltage; a frequency detector receivingthe oscillation signal, a first reference signal with a first frequency,and a second reference signal with a second frequency, wherein when thefrequency of the oscillation signal lies between the first frequency andthe second frequency, the frequency detector will output a high voltagecomparison signal, otherwise the frequency detector will output a lowvoltage comparison signal; a programmable counter receiving a clocksignal to trigger the counting and generating the digital code; aprogrammable controller receiving the high voltage comparison signal togenerate an enable signal directing the frequency detector to hold thehigh voltage comparison signal and directing the programmable counter tostop counting and hold the digital code; and a programmable memoryreceiving the enable signal to record the digital code.
 2. The digitaladjustable chip oscillator as claimed in claim 1, wherein the voltagecontrol oscillator is a relaxation oscillator.
 3. The digital adjustablechip oscillator as claimed in claim 1, wherein the reference voltagecircuit is a bandgap reference voltage circuit.
 4. The digitaladjustable chip oscillator as claimed in claim 1, wherein the voltageregulation circuit comprises: an operational transconductance amplifierreceiving the reference voltage, receiving a loop voltage, andoutputting a bias voltage; a transistor receiving the bias voltage,outputting a current, and outputting the operating voltage; and a loopcircuit receiving the current and outputting the loop voltage.
 5. Thedigital adjustable chip oscillator as claimed in claim 1, wherein thedigital tuning circuit comprises: a plurality of current mirrorsreceiving a bias voltage to generate a plurality of bias currentscorresponding to the bit of the digital code and receiving the operatingvoltage to stabilize the plurality of bias currents; a transistorreceiving the plurality of bias currents to generate the controlvoltage; and a plurality of switches coupled to the plurality of currentmirrors and the transistor and receiving the digital code to select theplurality of current mirrors.
 6. The digital adjustable chip oscillatoras claimed in claim 5, further comprising a prescaler receiving theoscillation signal and generating a period dividing signal according toa period dividing code.
 7. The digital adjustable chip oscillator asclaimed in claim 6, wherein the digital tuning circuit furthercomprises: an operational transconductance amplifier receiving thereference voltage, receiving a loop voltage, and outputting the biasvoltage; a transistor receiving the bias voltage, outputting a referencecurrent, and proportioning the bias current of the plurality of currentmirrors to the reference current wherein the bias voltage is coupled tothe plurality of current mirrors; and a loop circuit receiving thereference current and outputting the loop voltage.
 8. The digitaladjustable chip oscillator as claimed in claim 1, wherein the digitaltuning circuit further comprises: a plurality of charge current mirrorsreceiving a bias voltage to generate a plurality of bias currentscorresponding to the bit of the digital code and receiving the operatingvoltage to stabilize the plurality of bias currents; a plurality ofdischarge current mirrors receiving the bias current to generate aplurality of bias currents corresponding to the bit of the digital code;a transistor receiving the plurality of bias currents to generate thecontrol voltage; a plurality of first switches coupled to the pluralityof current mirrors and the transistor and receiving the digital code toselect the plurality of charge current mirrors; and a plurality ofsecond switches coupled to the plurality of current mirrors and thetransistor and receiving the digital code to select the plurality ofcharge current mirrors.
 9. The digital adjustable chip oscillator asclaimed in claim 1, wherein the programmable memory is a programmablefuse.
 10. The digital adjustable chip oscillator as claimed in claim 1,wherein the programmable memory is a programmable gate writer.
 11. Thedigital adjustable chip oscillator as claimed in claim 1, wherein thefrequency detector comprises: a first phase frequency detector receivingthe first reference signal, receiving the oscillation signal, andgenerating a first detection signal; a first low-pass filter receivingthe first detection signal and outputting the dc component of the firstdetection signal; a first comparator receiving the dc component of thefirst detection signal and generating a first comparison signal whereinwhen the first reference frequency lies above the oscillation frequency,the first comparison signal is high-level, otherwise the firstcomparison signal is low-level; a second phase frequency detectorreceiving the second reference signal, receiving the oscillation signal,and generating a second detection signal; a second low-pass filterreceiving the second detection signal and outputting the dc component ofthe second detection signal; a second comparator receiving the dccomponent of the second detection signal and generating a secondcomparison signal wherein when the second reference frequency lies abovethe oscillation frequency, the second comparison signal is high-level,otherwise the second comparison signal is low-level; and an exclusivegate receiving the first comparison signal, receiving the secondcomparison signal, and generating the comparison signal.
 12. The digitaladjustable chip oscillator as claimed in claim 11, wherein the firstlow-pass filter and the second low-pass filter are both switchcapacitance filters.
 13. The digital adjustable chip oscillator asclaimed in claim 1, wherein the voltage control oscillator and thedigital tuning circuit both have power save mode.
 14. A digitaladjustable chip oscillator, comprising: a voltage control oscillatorgenerating an oscillation signal, receiving a control voltage to adjustthe frequency of the oscillation signal, and receiving an operatingvoltage to stabilize the frequency of the oscillation signal; areference voltage circuit generating a reference voltage; a voltageregulation circuit receiving the reference voltage and generating theoperating voltage; and a digital tuning circuit receiving a digital codeto adjust the control voltage and receiving the operating voltage tostabilize the control voltage.
 15. The digital adjustable chiposcillator as claimed in claim 14, wherein the voltage controloscillator is a relaxation oscillator.
 16. The digital adjustable chiposcillator as claimed in claim 14, wherein the reference voltage circuitis a bandgap reference voltage circuit.
 17. The digital adjustable chiposcillator as claimed in claim 5, further comprising a prescalerreceiving the oscillation signal and generating a period dividing signalaccording to a period dividing code.
 18. The digital adjustable chiposcillator as claimed in claim 14, wherein the voltage regulationcircuit comprises: an operational transconductance amplifier receivingthe reference voltage, receiving a loop voltage, and outputting a biasvoltage; a transistor receiving the bias voltage, outputting a current,and outputting the operating voltage; and a loop circuit receiving thecurrent and outputting the loop voltage.
 19. The digital adjustable chiposcillator as claimed in claim 14, wherein the digital tuning circuitcomprises: a plurality of current mirrors receiving a bias voltage togenerate a plurality of bias currents corresponding to the bit of thedigital code and receiving the operating voltage to stabilize theplurality of bias currents; a transistor receiving the plurality of biascurrents to generate the control voltage; and a plurality of switchescoupled to the plurality of current mirrors and the transistor andreceiving the digital code to select the plurality of current mirrors.20. The digital adjustable chip oscillator as claimed in claim 14,wherein the digital tuning circuit further comprises: an operationaltransconductance amplifier receiving the reference voltage, receiving aloop voltage, and outputting the bias voltage; a transistor receivingthe bias voltage, outputting a reference current, and proportioning thebias current of the plurality of current mirrors to the referencecurrent wherein the bias voltage is coupled to the plurality of currentmirrors; and a loop circuit receiving the reference current andoutputting the loop voltage.
 21. The digital adjustable chip oscillatoras claimed in claim 14, wherein the digital tuning circuit furthercomprises: a plurality of charge current mirrors receiving a biasvoltage to generate a plurality of bias currents corresponding to thebit of the digital code and receiving the operating voltage to stabilizethe plurality of bias currents; a plurality of discharge current mirrorsreceiving the bias current to generate a plurality of bias currentscorresponding to the bit of the digital code; a transistor receiving theplurality of bias currents to generate the control voltage; a pluralityof first switches coupled to the plurality of current mirrors and thetransistor and receiving the digital code to select the plurality ofcharge current mirrors; and a plurality of second switches coupled tothe plurality of current mirrors and the transistor and receiving thedigital code to select the plurality of charge current mirrors.
 22. Thedigital adjustable chip oscillator as claimed in claim 14, wherein itfurther comprises: a frequency detector receiving the oscillationsignal, a first reference signal with a first frequency, and a secondreference signal with a second frequency, wherein when the oscillationfrequency lies between the first frequency and the second frequency, thefrequency detector will output a high voltage comparison signal,otherwise the frequency detector will output a low voltage comparisonsignal; a programmable counter receiving a clock signal to trigger thecounting and generating the digital code; a programmable controllerreceiving the high voltage comparison signal to generate an enablesignal directing the frequency detector to hold the high voltagecomparison signal and directing the programmable counter to stopcounting and hold the digital code; and a programmable memory receivingthe enable signal to record the digital code.
 23. The digital adjustablechip oscillator as claimed in claim 22, wherein the programmable memorycomprises: a plurality of decoders; and a plurality of poly-siliconfuses.
 24. The digital adjustable chip oscillator as claimed in claim22, wherein the programmable memory is a programmable gate writer. 25.The digital adjustable chip oscillator as claimed in claim 22, whereinthe frequency detector comprises: a first phase frequency detectorreceiving the first reference signal, receiving the oscillation signal,and generating a first detection signal; a first low-pass filterreceiving the first detection signal and outputting the dc component ofthe first detection signal; a first comparator receiving the dccomponent of the first detection signal and generating a firstcomparison signal wherein when the first reference frequency lies abovethe oscillation frequency, the first comparison signal is high-level,otherwise the first comparison signal is low-level; a second phasefrequency detector receiving the second reference signal, receiving theoscillation signal, and generating a second detection signal; a secondlow-pass filter receiving the second detection signal and outputting thedc component of the second detection signal; a second comparatorreceiving the dc component of the second detection signal and generatinga second comparison signal wherein when the second reference frequencylies above the oscillation frequency, the second comparison signal ishigh-level, otherwise the second comparison signal is low-level; and anexclusive gate receiving the first comparison signal, receiving thesecond comparison signal, and generating the comparison signal.
 26. Thedigital adjustable chip oscillator as claimed in claim 25, wherein thefirst low-pass filter and the second low-pass filter are both switchcapacitance filters.
 27. A digital adjustable chip oscillator,comprising: a voltage control oscillator generating an oscillationsignal and receiving a control voltage to control the frequency of theoscillation signal; a frequency-to-voltage converter receiving theoscillation signal and generating a loop voltage based on an operatingvoltage and a first voltage; an active comparison filter receiving theloop voltage, receiving a second voltage, and generating the controlvoltage; and a first programmable controller receiving a first digitalcode, receiving the operating voltage, and generating the secondvoltage.
 28. The digital adjustable chip oscillator as claimed in claim27, further comprising a reference voltage circuit generating thereference voltage wherein the reference voltage circuit is a bandgapreference voltage circuit.
 29. The digital adjustable chip oscillator asclaimed in claim 27, further comprising a voltage regulation circuitreceiving the reference voltage and generating the operating voltage.30. The digital adjustable chip oscillator as claimed in claim 27,wherein the voltage regulation circuit comprises: an operationaltransconductance amplifier receiving the reference voltage, receiving aloop voltage, and outputting a bias voltage; a transistor receiving thebias voltage, outputting a current, and outputting the operatingvoltage; and a loop circuit receiving the current and outputting theloop voltage.
 31. The digital adjustable chip oscillator as claimed inclaim 27, further comprising a prescaler receiving the oscillationsignal, generating a period dividing signal based on a period dividingcode, and outputting the a period dividing signal to thefrequency-to-voltage converter.
 32. The digital adjustable chiposcillator as claimed in claim 31, further comprising a delay circuitreceiving the period dividing signal, generating a delay signal, andoutputting the delay signal to the frequency-to-voltage converterwherein the operating period of the delay signal satisfies therequirement of the frequency-to-voltage converter.
 33. The digitaladjustable chip oscillator as claimed in claim 27, wherein the firstprogrammable controller comprises: a resistor serial having a pluralityof resistors, receiving the operating voltage, and generating the secondvoltage from the output end; a plurality of switches coupled to thecorresponding connection point of the plurality of resistors and theoutput end of the programmable controller; and a decoder receiving thefirst digital code to select the corresponding switch.
 34. The digitaladjustable chip oscillator as claimed in claim 27, wherein thefrequency-to-voltage converter comprises: a first capacitor; a secondcapacitor; an amplifier having an input end, a reversed-phase input end,and an output end wherein the input end of the amplifiers is coupled tothe first voltage; a third capacitor coupled to the reversed-phase inputend of the amplifier and the output end of the amplifier; a first switchcoupled to the input end of the frequency-to-voltage converter and thereversed-phase input end of the reversed-phase amplifier wherein thecontrol end of the first switch receives a signal having the phaseopposite to the phase of the oscillation signal; a second switch coupledto the reversed-phase input end of the reversed-phase amplifier and thesecond capacitor wherein the control end of the second switch receivesthe output signal of the voltage control oscillator; a voltage controlcurrent source coupled to the second capacitor wherein the input end ofthe voltage control current source receives the output end voltage ofthe reversed-phase amplifier and the output end of the voltage controlcurrent source generates a balance current; and a current-to-voltageconverter circuit of which the input end is coupled to the input end ofthe voltage control current source and the output end is coupled to aresistor wherein the current of the resistor is proportional to thebalance current.
 35. The digital adjustable chip oscillator as claimedin claim 27, wherein the digital adjustable chip oscillator furthercomprises a second programmable controller receiving a second digitalcode to select the input current of the resistor in thecurrent-to-voltage converter circuit.
 36. The digital adjustable chiposcillator as claimed in claim 35, wherein the second programmablecontroller comprises: a plurality of current mirrors wherein each biaspoint of the current mirrors is coupled to the input end of the voltagecontrol current source, the current generated by the output end of thevoltage control current source is a multiple of the balance current, andthe multiplication factor corresponds to the bit of the digital code;and a plurality of switches coupled to the output end of thecorrespondent above-mentioned plurality of current mirrors and theoutput end of the frequency-to-voltage converter and receiving thedigital code to select the plurality of current mirrors.
 37. The digitaladjustable chip oscillator as claimed in claim 27, wherein the activecomparison filter is a proportional integral filter.
 38. The digitaladjustable chip oscillator as claimed in claim 27, wherein the activecomparison filter comprises: a differential amplifier having an inputend, a reversed-phase input end, and an output end wherein the input endof the differential amplifier receives the second voltage a firstresistor of which one end receives the loop voltage and the other end iscoupled to the reversed-phase input end of the differential amplifier; afirst capacitor coupled to the reversed-phase input end of thedifferential amplifier and the output end of the differential amplifier;a second resistor of which one end is coupled to the reversed-phaseinput end of the differential amplifier; and a second capacitor coupledto the other end of the second resistor and the output end of thedifferential amplifier.
 39. The digital adjustable chip oscillator asclaimed in claim 27, further comprising a voltage limiter receiving thecontrol voltage output by the active comparison filter and limiting thecontrol voltage in the input range of the voltage control oscillator.40. The digital adjustable chip oscillator as claimed in claim 27,wherein the voltage control oscillator comprises a plurality ofdifferential delay units connected in the form of a ring wherein each ofthe differential delay unit has a control end to receive the controlvoltage and adjust the delay time, and has a pair of differential inputsand a pair of differential outputs.
 41. The digital adjustable chiposcillator as claimed in claim 40, wherein the voltage controloscillator further comprises a differential single-end converter havinga pair of differential inputs and a single-end output end wherein thepair of differential inputs of the differential single-end converter iscoupled to an output pair of the differential delay unit.
 42. Thedigital adjustable chip oscillator as claimed in claim 40, wherein thevoltage control oscillator further comprises an output buffer of whichthe input end is coupled to the single-end output end of thedifferential single-end converter, and the signal of the output end is afull amplitude signal.
 43. The digital adjustable chip oscillator asclaimed in claim 27, further comprising: a frequency detector receivingthe oscillation signal, a first reference signal with a first frequency,and a second reference signal with a second frequency, wherein when theoscillation frequency lies between the first frequency and the secondfrequency, the frequency detector will output a high voltage comparisonsignal, otherwise the frequency detector will output a low voltagecomparison signal; a programmable counter receiving a clock signal totrigger the counting and generating the first digital code; aprogrammable controller receiving the high voltage comparison signal togenerate an enable signal directing the frequency detector to hold thehigh voltage comparison signal and directing the programmable counter tostop counting and hold the digital code; and a programmable memoryreceiving the enable signal to record the digital code.
 44. The digitaladjustable chip oscillator as claimed in claim 43, wherein theprogrammable memory is a programmable fuse.
 45. The digital adjustablechip oscillator as claimed in claim 1, wherein the programmable memoryis a programmable gate writer.
 46. The digital adjustable chiposcillator as claimed in claim 27, further comprising: a frequencydetector receiving the oscillation signal, a first reference signal witha first frequency, and a second reference signal with a secondfrequency, wherein when the oscillation frequency lies between the firstfrequency and the second frequency, the frequency detector will output ahigh voltage comparison signal, otherwise the frequency detector willoutput a low voltage comparison signal; a programmable counter receivinga clock signal to trigger the counting and generating the first digitalcode and the second digital code; a programmable controller receivingthe high voltage comparison signal to generate an enable signaldirecting the frequency detector to hold the high voltage comparisonsignal and directing the programmable counter to stop counting and holdthe first digital code and the second digital code; and a programmablememory receiving the enable signal to record the first digital code andthe second digital code.
 47. The digital adjustable chip oscillator asclaimed in claim 43, wherein the frequency detector comprises: a firstphase frequency detector receiving the first reference signal, receivingthe oscillation signal, and generating a first detection signal; a firstlow-pass filter receiving the first detection signal and outputting thedc component of the first detection signal; a first comparator receivingthe dc component of the first detection signal and generating a firstcomparison signal wherein when the first reference frequency lies abovethe oscillation frequency, the first comparison signal is high-level,otherwise the first comparison signal is low-level; a second phasefrequency detector receiving the second reference signal, receiving theoscillation signal, and generating a second detection signal; a secondlow-pass filter receiving the second detection signal and outputting thedc component of the second detection signal; a second comparatorreceiving the dc component of the second detection signal and generatinga second comparison signal wherein when the second reference frequencylies above the oscillation frequency, the second comparison signal ishigh-level, otherwise the second comparison signal is low-level; and anexclusive gate receiving the first comparison signal, receiving thesecond comparison signal, and generating the comparison signal.
 48. Thedigital adjustable chip oscillator as claimed in claim 47, wherein thefirst low-pass filter and the second low-pass filter are both switchcapacitance filters.
 49. A digital adjustable chip oscillator,comprising: a voltage control oscillator generating an oscillationsignal and receiving a control voltage to control the frequency of theoscillation signal; a frequency-to-voltage converter receiving theoscillation signal and generating a loop voltage based on an operatingvoltage and a first voltage; an active comparison filter receiving theloop voltage, receiving a second voltage, and generating the controlvoltage; and a first programmable controller receiving a first digitalcode, receiving the operating voltage, and generating the secondvoltage. a frequency detector receiving the oscillation signal, a firstreference signal with a first frequency, and a second reference signalwith a second frequency, wherein when the frequency of the oscillationsignal lies between the first frequency and the second frequency, thefrequency detector will output a high voltage comparison signal,otherwise the frequency detector will output a low voltage comparisonsignal; a programmable counter receiving a clock signal to trigger thecounting and generating the first digital code; a programmablecontroller receiving the high voltage comparison signal to generate anenable signal directing the frequency detector to hold the high voltagecomparison signal and directing the programmable counter to stopcounting and hold the first digital code; and a programmable memoryreceiving the enable signal to record the first digital code.
 50. Thedigital adjustable chip oscillator as claimed in claim 49, furthercomprising a reference voltage circuit generating the reference voltagewherein the reference voltage circuit is a bandgap reference voltagecircuit.
 51. The digital adjustable chip oscillator as claimed in claim49, further comprising a voltage regulation circuit receiving thereference voltage and generating the operating voltage.
 52. The digitaladjustable chip oscillator as claimed in claim 49, wherein the voltageregulation circuit comprises: an operational transconductance amplifierreceiving the reference voltage, receiving a loop voltage, andoutputting a bias voltage; a transistor receiving the bias voltage,outputting a current, and outputting the operating voltage; and a loopcircuit receiving the current and outputting the loop voltage.
 53. Thedigital adjustable chip oscillator as claimed in claim 49, wherein thefirst programmable controller comprises: a resistor serial having aplurality of resistors, receiving the operating voltage, and generatingthe second voltage from the output end; a plurality of switches coupledto the corresponding connection point of the plurality of resistors andthe output end of the programmable controller; and a decoder receivingthe first digital code to select the corresponding switch.
 54. Thedigital adjustable chip oscillator as claimed in claim 49, wherein thefrequency-to-voltage converter comprises: a first capacitor; a secondcapacitor; an amplifier having an input end, a reversed-phase input end,and an output end wherein the input end of the amplifiers is coupled tothe first voltage; a third capacitor coupled to the reversed-phase inputend of the amplifier and the output end of the amplifier; a first switchcoupled to the input end of the frequency-to-voltage converter and thereversed-phase input end of the reversed-phase amplifier wherein thecontrol end of the first switch receives a signal having a phaseopposite to the phase of the oscillation signal; a second switch coupledto the reversed-phase input end of the reversed-phase amplifier and thesecond capacitor wherein the control end of the second switch receivesthe output signal of the voltage control oscillator; a voltage controlcurrent source coupled to the second capacitor wherein the input end ofthe voltage control current source receives the output end voltage ofthe reversed-phase amplifier and the output end of the voltage controlcurrent source generates a balance current; and a current-to-voltageconverter circuit of which the input end is coupled to the input end ofthe voltage control current source and the output end is coupled to aresistor wherein the current of the resistor is proportional to thebalance current.
 55. The digital adjustable chip oscillator as claimedin claim 49, further comprising a prescaler receiving the oscillationsignal, generating a period dividing signal based on a period dividingcode, and outputting the period dividing signal to thefrequency-to-voltage converter.
 56. The digital adjustable chiposcillator as claimed in claim 55, further comprising a delay circuitreceiving the period dividing signal, generating a delay signal, andoutputting the delay signal to the frequency-to-voltage converterwherein the operating period of the delay signal satisfies therequirement of the frequency-to-voltage converter.
 57. The digitaladjustable chip oscillator as claimed in claim 49, further comprising asecond programmable controller receiving a second digital code to selectthe input current of the resistor in the current-to-voltage convertercircuit.
 58. The digital adjustable chip oscillator as claimed in claim57, wherein the second programmable controller comprises: a plurality ofcurrent mirrors wherein each bias point of the current mirrors iscoupled to the input end of the voltage control current source, thecurrent generated by the output end of the voltage control currentsource is a multiple of the balance current, and the multiplicationfactor corresponds to the bit of the digital code; and a plurality ofswitches coupled to the output end of the correspondent above-mentionedplurality of current mirrors and the output end of thefrequency-to-voltage converter and receiving the digital code to selectthe plurality of current mirrors.
 59. The digital adjustable chiposcillator as claimed in claim 49, wherein the active comparison filteris a proportional integral filter.
 60. The digital adjustable chiposcillator as claimed in claim 49, wherein the active comparison filtercomprises: a differential amplifier having an input end, areversed-phase input end, and an output end wherein the input end of thedifferential amplifier receives the second voltage a first resistor ofwhich one end receives the loop voltage and the other end is coupled tothe reversed-phase input end of the differential amplifier; a firstcapacitor coupled to the reversed-phase input end of the differentialamplifier and the output end of the differential amplifier; a secondresistor of which one end is coupled to the reversed-phase input end ofthe differential amplifier; and a second capacitor coupled to the otherend of the second resistor and the output end of the differentialamplifier.
 61. The digital adjustable chip oscillator as claimed inclaim 49, further comprising a voltage limiter receiving the controlvoltage output by the active comparison filter and limiting the controlvoltage in the input range of the voltage control oscillator.
 62. Thedigital adjustable chip oscillator as claimed in claim 49, wherein thevoltage control oscillator comprises a plurality of differential delayunits connected in the form of a ring wherein each of the differentialdelay unit has a control end to receive the control voltage and adjustthe delay time, and has a pair of differential inputs and a pair ofdifferential outputs.
 63. The digital adjustable chip oscillator asclaimed in claim 62, wherein the voltage control oscillator furthercomprises a differential single-end converter having a pair ofdifferential inputs and a single-end output end wherein the pair ofdifferential inputs of the differential single-end converter is coupledto an output pair of the differential delay unit.
 64. The digitaladjustable chip oscillator as claimed in claim 63, wherein the voltagecontrol oscillator further comprises an output buffer of which the inputend is coupled to the single-end output end of the differentialsingle-end converter, and the signal of the output end is a fullamplitude signal.
 65. The digital adjustable chip oscillator as claimedin claim 49, wherein the programmable memory is a programmable fuse. 66.The digital adjustable chip oscillator as claimed in claim 49, whereinthe programmable memory is a programmable gate writer.
 67. The digitaladjustable chip oscillator as claimed in claim 49, wherein the frequencydetector comprises: a first phase frequency detector receiving the firstreference signal, receiving the oscillation signal, and generating afirst detection signal; a first low-pass filter receiving the firstdetection signal and outputting the dc component of the first detectionsignal; a first comparator receiving the dc component of the firstdetection signal and generating a first comparison signal wherein whenthe first reference frequency lies above the oscillation frequency, thefirst comparison signal is high-level, otherwise the first comparisonsignal is low-level; a second phase frequency detector receiving thesecond reference signal, receiving the oscillation signal, andgenerating a second detection signal; a second low-pass filter receivingthe second detection signal and outputting the dc component of thesecond detection signal; a second comparator receiving the dc componentof the second detection signal and generating a second comparison signalwherein when the second reference frequency lies above the oscillationfrequency, the second comparison signal is high-level, otherwise thesecond comparison signal is low-level; and an exclusive gate receivingthe first comparison signal, receiving the second comparison signal, andgenerating the comparison signal.
 68. The digital adjustable chiposcillator as claimed in claim 67, wherein the first low-pass filter andthe second low-pass filter are both switch capacitance filters.